This invention relates generally to voltage reference generation circuits, and more particularly, it relates to a new and improved reference voltage generation circuit used in gate oxide protected circuits for generating an NMOS reference voltage and a PMOS reference voltage, which are independent of an I/O buffer power supply voltage.
As is generally well-known in the art of modern digital integrated circuits, especially those manufactured in accordance with complementary metal-oxide-semiconductor (CMOS) technology, the reliability and performance of the circuit operation is frequently determined by the availability of a stable reference voltage. There are many types of functional circuits internal to an integrated circuit which require stable reference voltages in order to operate properly and effectively. Such functional circuits may include operational amplifiers, inverter circuits, level shifting circuits, output driver circuits, memory circuits, microprocessors, logic gate circuits, input/output driver circuits, and I/O buffer circuits.
These various functional circuits on the first integrated circuit will typically be used to generate output signals which communicate with another second integrated circuit, that is powered by a power supply voltage having a predetermined voltage level higher than a supply potential applied to the first integrated circuit. For example, the supply potential applied to the functional circuits may normally be only +2.0 volts with respect to a ground potential. On the other hand, the second integrated circuit receiving the output signals from the functional circuits may have a power supply voltage of +3.3 volts. In order to accommodate for this communication with the second integrated circuit, the supply potential applied to the functional circuits must be increased to or near +3.3 volts.
However, in view of the development made in CMOS technologies, the thickness of the transistor gate oxide for forming the CMOS devices are becoming thinner and thinner. In the typical semiconductor process, when the thickness of the gate oxide is reduced to approximately 60 .ANG. (angstroms) or below, a voltage difference higher than about +2.4 volts-+2.5 volts applied across the gate oxide of the transistor device will cause a breakdown of the gate oxide to occur, thereby resulting in a failure of the functional circuits. In order to overcome this problem, there have been provided in the prior art, gate oxide protection circuits utilizing plurality of PMOS and NMOS transistors so as to limit the voltage difference at the gate oxide to be below a breakdown voltage magnitude.
In co-pending application Ser. No. 08/599,898 filed on Feb. 12, 1996, and entitled "Gate Oxide Voltage Limiting Devices for Digital Circuits," which is assigned to the same assignee as the present invention, there is illustrated in FIG. 4 a gate oxide protected inverting level shifter 4', which includes PMOS transistors L.sub.P1, L.sub.P2, and L.sub.P5 and NMOS transistor L.sub.N2. The gates of the PMOS transistors are connected to a PMOS reference voltage V.sub.refp, and the gate of the NMOS transistor is connected to an NMOS reference voltage V.sub.refn. In FIG. 5, there is depicted a gate oxide protected inverter 2', which includes PMOS transistors I.sub.P1 and I.sub.P3 whose gates are connected to reference voltage V.sub.refp and NMOS transistor I.sub.N1 and I.sub.N2 whose gates are connected to reference voltage V.sub.refn. Further, there is shown in FIG. 8 an I/O buffer which includes a gate protected output driver circuit 6' formed of a PMOS transistor D.sub.P2 and an NMOS transistor D.sub.N2. The gate of the transistor D.sub.P2 is connected to reference voltage V.sub.refp, and the gate of transistor D.sub.N2 is connected to reference voltage V.sub.refn.
Each of the inverting level shifter, inverter, and output driver circuit is powered by an upper predetermined I/O supply voltage V.sub.CCIO and a lower predetermined power supply voltage V.sub.SSIO, where V.sub.CCIO =+3.3 V and V.sub.SSIO =0 V. Assuming that the gate oxide thickness is about 60 angstroms, and the gate oxide breakdown voltage is about +2.4V-+2.5 V, then the reference voltage V.sub.refp may be equal to about +1.1 V and the reference voltage V.sub.refn may be about +2.2 V.
The inventors of the present invention have developed a reference voltage generation scheme for generating the reference voltages V.sub.refn and V.sub.refp for gate oxide protected circuits. The reference voltage V.sub.refn is independent of the upper predetermined I/O supply voltage V.sub.CCIO. The reference voltage V.sub.refp is always a constant voltage below the supply voltage V.sub.CCIO, independent of the voltage between V.sub.CCIO and V.sub.SSIO. In this way the gate-to-source voltage, which is the principal control mechanism for a MOS device, remains constant for both PMOS and NMOS devices, no matter what the value of V.sub.CCIO is. The instant reference voltage generation circuit is comprised of a bandgap reference voltage, a first operational amplifier, a voltage divider, and a second operational amplifier.